Improving SoC design flows with embedded memory models: Jay Abraham describes a methodology for accurate and complete timing and power model generation

摘要

Practically all digital System on Chip (SoC) designs contain embedded ROM, RAM, or register file memories of various sizes. These types of embedded memory on average consume 30 - 50 percent of die area and this percentage is growing at an astounding 25 percent annually. With so many designs containing memory devices, on-chip critical timing paths will either start or end at memory address, data, or control pins.