Utilization of relieved corners from multi-corner libraries in deterministic static timing analysis

摘要

This paper proposes an efficient approach to deterministic static timing analysis, which uses relieved corner values for timing components of each gate to avoid the pessimistic estimates of the system delay. The candidates of the relieved corner values for timing components such as gate delay and output slew are sampled in terms of the input slew and the output capacitance, which composes the multi-corner libraries. Then, the relieved corner values are adaptively selected so that the estimate of the system delay will match the user defined target percentile point. In experiments, the proposed method estimated the corner of the system delay with the error 0.27% on average, compared to MC simulation results. In runtime evaluation, the proposed method achieved ×4,181 speedup on average compared to MC simulation.