Library characterization and 'Static Timing Analysis' (STA) are widely used in the design of modern CMOS integrated circuits to confirm that critical timing constraints are met. While many commercial tools are available to do timing validation using library characterization and static timing analysis, their operation depends on calculations relative to a global synchronous clock. This thesis applies timing validation to circuits from which the global synchronous clock is absent, making application of commercial tools difficult. Previous work at the University of Southern California (USC) showed how to overcome the incompatibility of commercial STA tools for asynchronous circuits. This thesis shows how to overcome the incompatibility of library characterization for asynchronous circuits, and ties the results to the STA solution of USC.;The particular family of circuits considered in this thesis is called GasP. GasP circuits are light in area and power, and have demonstrated operation at about twice the throughput one would expect from conventional clocked circuits. This makes GasP an ideal candidate for modern network-on-chip and system-on-chip architectures. In part, GasP circuits achieve their performance advantages by using a 'single-track' signaling protocol. Two GasP modules communicate with each other over a single wire. One module drives the wire up and a second module at the other end of the wire drives the wire down. This conflicts with the common assumption that wires are driven only from one end. As a result, special circuitry is needed to characterize a GasP library module. This thesis shows how to break a GasP module and its timing constraints into manageable pieces and how to simulate and collect the data relevant for characterization and static timing analysis. When combined with software tools for identifying the critical timing constraints, these thesis results will provide confidence in the correct operation of GasP.
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