Parasitic Inductance Design Considerations to Suppress Gate Voltage Oscillation of Fast Switching Power Semiconductor Devices

摘要

Fast switching power semiconductor devices such as SiC MOSFET and GaN FET have attracting increasing attention because of superior switching capability which contributes to high efficiency and high power density of power converters. However, fast switching capability generates large switching noise. Particularly, parasitic oscillation observed in the gate voltage is a severe problem due to the gate-source breakdown. This paper hypothesized that the gate resonator selectively takes in parasitic oscillation caused by a power circuit because of its frequency characteristic and analyzed the gate voltage oscillation. As a result, the phenomenon is characterized by an oscillation susceptibility which indicates susceptibility of the gate voltage to a drain voltage oscillation. Moreover, the oscillation susceptibility predicts the parasitic inductance dependency of the gate voltage oscillation. Therefore, the parasitic inductance should be designed to suppress this oscillation considering the oscillation susceptibility. Results obtained by simulation and experiment indicated appropriateness of analysis results.