首页> 外文会议>International Conference on Computer and Knowledge engineering >A performance counter-based control flow checking technique for multi-core processors
【24h】

A performance counter-based control flow checking technique for multi-core processors

机译:基于性能计数器的多核处理器控制流检查技术

获取原文

摘要

Today, both the rapid improvement of process technology and the arrival of new embedded systems with high-performance requirements, have led to making the current trend in processors manufacturing shift from single-core processors to multi-core processors. This trend has raised several challenges for reliability in safety-critical systems that operate in high-risk environments, making them more vulnerable to soft errors. Hence, using additional methods to satisfy the strict system requirements in terms of safety and reliability is unavoidable. In this paper, an efficient hybrid method to detect control flow errors in multi-core processors has been proposed and evaluated. About 36,000 software faults have been injected into three well-known multi-threaded benchmarks at run-time. The experiment results show that the fault coverage is 100%. The results also show that the execution time overhead varies between 31.25% and 51.02%, and the program size overhead varies between 20.23% and 67.64% with respect to the employed benchmark.
机译:如今,制程技术的飞速发展和具有高性能要求的新型嵌入式系统的出现,都导致当前的处理器制造趋势已从单核处理器转向多核处理器。这种趋势对在高风险环境中运行的安全关键型系统的可靠性提出了若干挑战,使其更容易受到软错误的影响。因此,不可避免地要使用额外的方法来满足严格的系统要求,包括安全性和可靠性。本文提出并评估了一种有效的混合方法来检测多核处理器中的控制流错误。在运行时,大约36,000个软件故障已注入三个著名的多线程基准测试中。实验结果表明,故障覆盖率为100%。结果还显示,相对于所采用的基准,执行时间开销在31.25%至51.02%之间变化,程序大小开销在20.23%至67.64%之间变化。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号