Implementation of MPEG codec system Based on FPGA and Upper Computer

摘要

Due to the huge amount of calculations of video compression, its implementation needs the support of powerful computing capability. This article briefly describes the principles and key technologies of MPEG-1, and proposes an implementation method of MPEG-1 codec system based on FPGA and upper computer. The MPEG-1 encoding is implemented in FPGA, meanwhile, the adding of HDLC protocol to the compressed data is also finished in FPGA. The compressed code stream with HDLC protocol is transmitted by RS485 bus. Then the upper computer receives compressed code stream data by MPB202 card, which can parse data with HDLC protocol. Finally, the upper computer gets the compressed image data, decodes the compressed data and displays the image. After verification, the system can successfully realize the MPEG-1 encoding and decoding. This system can be used as a basic reference to a more advanced video compression system.