Design of parallel hardware neural network systems from customanalog VLSI `building block' chips

摘要

Hardware to implement feedforward neural networks has beenndeveloped for the evaluation of learning algorithms and prototyping ofnapplications. To allow the construction of networks with arbitrarynarchitectures, CMOS VLSI building-block components (e.g. arrays ofnneurons and synapses) have been designed. These can be cascaded to formnnetworks with hundreds of neurons per layer. A 64-channel multiplexerninput neuron chip serves to buffer stored charges for injection into thenfirst synaptic layer. A 32×32 synapse chip design uses multiplierncircuits to generate a conductance from stored analog chargesnrepresenting weights. A 32-channel variable-gain neuron chip applies annadjustable-gain sigmoidal activation function to the sum of currentsnfrom the previous synaptic layer. Learning is performed by a hostncomputer that can download weights and inputs onto the feedforwardnhardware, and read resultant network outputs. Weights and input valuesnare stored as charges on on-chip capacitors; these are serially andninvisibly refreshed by off-chip circuits that convert values stored inndigital memory into analog signals