首页> 外文会议>Integrated circuit and system design : Power and timing modeling, optimization and simulation >An On-Chip Multi-mode Buck DC-DC Converter for Fine-Grain DVS on a Multi-power Domain SoC Using a 65-nm Standard CMOS Logic Process
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An On-Chip Multi-mode Buck DC-DC Converter for Fine-Grain DVS on a Multi-power Domain SoC Using a 65-nm Standard CMOS Logic Process

机译:片上多模式降压DC-DC转换器,用于采用65nm标准CMOS逻辑工艺的多电源域SoC上的细粒度DVS

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摘要

In this paper, we propose an on-chip dc-dc buck converter for fine-grain dynamic voltage scaling (DVS) on a multi-power domain SoC. The proposed circuit converts from the I/O voltage to the required core operating voltage. This regulator is equipped with the programmable output buffer and the switching signal modulator according to the mod ule operating condition. The proposed converter is fabricated with a 65-nm standard CMOS logic process within the area of 5 bonding pads. The maximum power efficiency is over 88%, and the leakage current in the deep stand-by mode is measured only 19 nA.
机译:在本文中,我们提出了一种片上DC-DC降压转换器,用于在多电源域SoC上实现细粒度动态电压缩放(DVS)。所提出的电路将I / O电压转换为所需的内核工作电压。该稳压器根据模块的工作条件配备了可编程输出缓冲器和开关信号调制器。拟议的转换器在5个焊盘的区域内采用65 nm标准CMOS逻辑工艺制造。最大功率效率超过88%,深度待机模式下的泄漏电流仅为19 nA。

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