fpgaEva: A Logic-Level Architecture Evaluator for SRAM-Based FPGAs

摘要

The programmable logic device (PLD) industry has experienced an exponential growth in the past fifteen years. With the rapid development of the programmable logic architectures, the PLD (especially the field programmable gate array (FPGA) synthesis tools and algorithms have also made significant progress. Automatic synthesis tools are widely used in FPGA designs due to the rapid increase of FPGA complexity. Therefore, the increasing demands of high-density and high-performance FPGA designs and short compilation/synthesis time require that the FPGA architecture development process to be tightly coupled with the advanced synthesis technologies. In this paper, we present a logic-level architecture evaluator, named fpgaEva, for SRAM-based FPGAs. fpgaEva is targeted for heterogeneous and hierarchical FPGA architectures, including (i) FPGAs with heterogeneous look-up tables (LUTs) (ii) FPGAs with embedded memory blocks (EMBs) (iii) LUT cluster based FPGAs and (iv) FPGAs with complex programmable logic blocks (PLBs). It incorporates the state-of-the-art synthesis algorithms and techniques and has a user friendly Java-based GUI (Graphical User Interface). Together, they form an integrated and flexible FPGA architecture evaluation system.