Department of Electronics Engineering, Indian Institute of Technology (BHU), Varanasi-221005, India;
Department of Electronics Engineering, Indian Institute of Technology (BHU), Varanasi-221005, India;
Department of Electronics Engineering, Indian Institute of Technology (BHU), Varanasi-221005, India;
Department of Electronics Engineering, Indian Institute of Technology (BHU), Varanasi-221005, India;
Department of Electronics Engineering, Indian Institute of Technology (BHU), Varanasi-221005, India;
Department of Electronics Engineering, Indian Institute of Technology (BHU), Varanasi-221005, India;
Doping profiles; Logic gates; Threshold voltage; Transistors; Economic indicators; Semiconductor process modeling;
机译:具有垂直高斯型掺杂分布的短沟道双栅金属氧化物半导体场效应晶体管的亚阈值摆幅的二维模型
机译:具有垂直高斯型掺杂轮廓的短沟道双栅金属氧化物半导体场效应晶体管的电势分布和阈值电压的二维模型
机译:具有垂直高斯型掺杂轮廓的短沟道双栅金属氧化物半导体场效应晶体管的电势分布和阈值电压的二维模型
机译:具有垂直高斯掺杂型材的双栅极连接场效应晶体管性能评价
机译:双掺杂双应变调制掺杂场效应晶体管:3D-SMODFET。
机译:单轴应变对双栅石墨烯纳米带场效应晶体管性能影响的分析模型
机译:双栅极连接隧洞场效应晶体管性能分析:RF稳定性视角