Design and Verification of SRAM Self-Detection Repair Based on ECC and BISR Circuit

摘要

In the space radiation environment, the chip in the spacecraft is susceptible to radiation effects, which leading to the errors of the device. Therefore, the detection and repair of the errors is particularly important. Aiming at the soft and hard errors of memory cell caused by single event effect in space radiation environment, a memory architecture based on ECC circuit and BISR circuit is proposed to detect errors online, distinguish between soft and hard errors and repair them, so as to reduce the accumulation of errors. And the memory structure uses repair circuit and redundant memory to repair soft errors and hard errors respectively. The simulation results show that in normal read-write mode, the proposed memory structure not only can repair soft errors, but also can repair hard errors, and can detect unrepairable hard errors. It means that the proposed method is effective. when the memory size is 39 x 64K, the area of the ECC and the BIRA circuit is about 13.95% of the entire memory chip.