A Novel scheme of High-Speed Phase-Frequency Detector for Low-Power Low-Phase noise PLL Design

摘要

Phase-Frequency Detectors are commonly used in Phase-Locked Loop circuits, which they have been applied in many high-speed designs such as microprocessors and communication systems. In this work, a new structure of Phase-Frequency Detector (PDF1) is proposed to overcome the frequency limitations and the dead zone of the conventional design. The proposed PFD has been designed in Cadence virtuoso environment and implemented using 130 nm technology with a supply voltage of one Volt (1V). The results show excellent agreement with computer simulations, and significant reduction in area and power dissipation was observed, also the reset path has been completely removed in this design.