Design of 2#x00D7;VDD logic gates with only 1#x00D7;VDD devices in nanoscale CMOS technology

摘要

The novel 2×VDD NOT, NAND, and NOR logic gates have been designed and implemented in a nanoscale CMOS process with only 1×VDD devices. With the proposed dynamic source bias technique, the logic gates can be designed to have 2×VDD tolerant capability. Thus, the new 2×VDD logic gates can be operated under 2×VDD voltage environment without suffering the gate-oxide reliability issue.