Designing semiconductor products increasingly involves trade-offs in cost, power, performance, and supply noise. While geometries continue to shrink, voltages no longer scale so requirements for managing supply noise become more stringent. Traditional design approaches using oxide decoupling capacitors improve performance by reducing supply noise, but result in increased area and leakage. As an alternative to oxide decoupling capacitors, this paper explores the cost, noise reduction, and leakage advantages seen in representative IBM 90 nm and 65 nm ASIC Products through use of efficient trench decoupling capacitors.
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