机译:优化3D电路中的去耦电容器以实现电网完整性
Univ. of Minnesota, Twin Cities, Minneapolis, MN, USA;
CMOS integrated circuits; MIM devices; integrated circuit design; power supply circuits; 2D chips; 3D IC design; 3D chips; 3D circuits; CMOS decaps; MIM decaps; congestion-aware 3D power supply network optimization algorithm; decoupling capacitor optimisation; metal insulator-metal decaps; metal interconnects; power grid integrity; power grid optimization; power integrity problem; routing blockages; sequence-of-linear-programs-based method; 3D integration; CMOS decap; MIM decap; decoupling capacitors; design and test; power grid;
机译:用于I / O电源完整性的高效封装内去耦电容器优化
机译:用于数字IC电源调节的有源去耦电容电路的设计与实现
机译:Krylov-subspace技术优化印刷电路板上去耦电容器位置的方法
机译:使用MIM和CMOS解耦电容器对3D电路进行拥塞感知的电网优化
机译:具有用于纳米级集成电路的片上去耦电容器的高性能配电网络
机译:基于电容电路的高选择性高灵敏度自供电式葡萄糖传感器
机译:三维电路中的电网优化采用mIm和CmOs去耦电容