Application of EUV resolution enhancement techniques (RET) to optimize and extend single exposure bi-directional patterning for 7nm and beyond logic designs

摘要

EUV lithography is uniquely positioned to extend single exposure solutions for critical imaging layers at the 7 nm technology node and beyond. In this work, we demonstrate the application of advanced EUV resolution enhancement techniques to enable bidirectional printing of 36 and 32 nm pitch standard logic cell and SRAM designs with 0.33 NA optics using an EUV OPC model. Prior work has highlighted the issues of pattern placement errors and image contrast loss due to the non-telecentricity that is inherent in EUV reflective imaging systems and masks. This work has also demonstrated utilizing asymmetric pupil to reduce the pattern placement error. It has been previously shown that there is a potential reduction in common process window due to through-pitch best focus shifts with non-optimized SRAF placement. In this paper, we demonstrate the use of: pattern placement error aware SMO, asymmetric illumination shape, and SRAF placement optimization to increase the overall common process window by as much as 40% compared to OPC only optimization. Consequently, we demonstrate the improved post-RET single patterning solution for 0.33 NA EUV bi-directional 7 nm node logic designs. We show that these techniques can achieve the required performance for MEEF, best focus shift across features, and ILS, which is known to be important for reducing stochastics and subsequent line-edge-roughness (LER).