In this paper, we present a method for diagnosing gate delay faults in synchronous sequential circuits. This method is an outgrowth of our previous work on delay fault diagnosis in combinational circuits, and is therefore based on a path tracing algorithm appropriate for sequential circuits. Input data for diagnosis are (1) the gate level description of the circuit, (2) the set of test sequences, and (3) the set of failing patterns and failing outputs provided by the tester. Output data are a set of potential fault locations. In order to correctly interpret the tester results, and avoid multiple fault effects and self-masking problems during diagnostic processing, each test sequence is considered under different combinations of slow and fast clock cycles (slow clock test methodology). Experimental results are given to show the feasibility, reliability and efficiency of the diagnosis method.
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