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STUCK-FAULT DIAGNOSIS METHOD FOR VARIABLE DELAY CONTROL CIRCUIT AND MEMORY CONTROLLER WITH VARIABLE DELAY CONTROL CIRCUIT

机译:可变时延控制电路的停顿故障诊断方法及带有可变时延控制电路的存储器控​​制器

摘要

PROBLEM TO BE SOLVED: To make a diagnosis, in a shorter test time than before, as to presence or absence of a stuck fault which has occurred in a variable delay control circuit.SOLUTION: A stuck-fault diagnosis method for a variable delay control circuit comprises: switching the number of connections of a delay circuit which transfers data signals by plural switch circuits, depending on a control value received from plural control registers via plural control lines; calculating an exclusive logical OR of logical values appearing on two control lines of the plural control lines by each of plural exclusive OR circuits; retaining the logical values output from the exclusive OR circuits in plural diagnosis registers; setting the control registers to logical 0 in a variable delay control circuit which calculates a logical OR of the logical values output from the exclusive OR circuits, by an OR circuit; detecting a stuck fault of a logical 1 which has occurred in one of the control lines, based on the logical value output from the OR circuit; setting the control registers to logical 1; and detecting a stuck fault of a logical 0 which has occurred in one of the control lines, based on the logical value output from the OR circuit.SELECTED DRAWING: Figure 1
机译:解决的问题:要比以前更短的测试时间来诊断是否存在可变延迟控制电路中发生的卡死故障解决方案:用于可变延迟控制的卡死故障诊断方法该电路包括:根据经由多个控制线从多个控制寄存器接收的控制值,切换通过多个开关电路传输数据信号的延迟电路的连接数;通过多个异或电路分别计算在多条控制线的两条控制线上出现的逻辑值的异或逻辑;从异或电路输出的逻辑值保留在多个诊断寄存器中;在可变延迟控制电路中将控制寄存器设置为逻辑0,该可变延迟控制电路通过“或”电路计算从异或电路输出的逻辑值的逻辑“或”;基于从或电路输出的逻辑值,检测在控制线之一中发生的逻辑1的卡死故障;将控制寄存器设置为逻辑1;并基于从或电路输出的逻辑值,检测在控制线之一中发生的逻辑0的故障。

著录项

  • 公开/公告号JP2017040532A

    专利类型

  • 公开/公告日2017-02-23

    原文格式PDF

  • 申请/专利权人 FUJITSU LTD;

    申请/专利号JP20150161817

  • 发明设计人 HASHIMOTO MICHITAKA;

    申请日2015-08-19

  • 分类号G01R31/28;H03K5/131;H03K5/133;G11C29/56;

  • 国家 JP

  • 入库时间 2022-08-21 14:00:43

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