首页> 外文会议>Electronics Packaging Technology Conference (EPTC), 2011 IEEE 13th >Cu wire bonding for fine pitch 40nm circuit under pad silicon integrated circuits: Development of a comprehensive robust Cu wire bonding process
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Cu wire bonding for fine pitch 40nm circuit under pad silicon integrated circuits: Development of a comprehensive robust Cu wire bonding process

机译:焊盘硅集成电路下用于细间距40nm电路的铜线键合:全面,强大的铜线键合工艺的发展

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摘要

Historically Cu wire has been targeted to lower pin count high power discrete devices and consumer product for a long time. As gold costs increased the industry started focusing on moving more mainstream products to Cu wire. Markets that have seen the largest growth in Cu wire bonded products include consumer electronics, communication devices and industrial electronics etc. However, Cu wire has been used sparingly in high reliability markets which require stringent and extensive reliability performance. One of the reasons is that the leading edge silicon nodes with low-k/ELK device bonding pads are vulnerable to damage during wire bond process even with gold wire. In this manuscript our work on the development of a comprehensive protocol, experimental procedure and exhaustive characterization of a highly reliable Cu wire bonding process and bill of materials for use on wire bond devices made in leading edge silicon node technologies is summarized. Included in the work was the application of this development process to multiple aspects of the overall process and materials selection including but not limited to: i) Cu wire bond process development at five different manufacturing locations owned by three different assembly suppliers; ii) three different mold compounds; iii) three different package types; and iv) multiple integrated circuit designs, all with circuit under pad. Also summarized are the extensive reliability evaluations that were completed through the course of this work. Using these exhaustive protocols, experimental procedures, characterizations and reliability studies, we successfully developed a robust bond pad design, which in combination with the wire bond process and bill of materials results in highly reliable Cu wire bonded devices in advanced silicon technology nodes.
机译:长期以来,铜线一直以低引脚数的高功率分立器件和消费类产品为目标。随着金成本的增加,该行业开始集中精力将更多主流产品转移到铜丝上。铜线键合产品增长最快的市场包括消费类电子产品,通信设备和工业电子产品等。然而,铜线已很少用于要求严格而广泛的可靠性能的高可靠性市场。原因之一是带有低k / ELK器件键合焊盘的前沿硅节点即使在金线焊接过程中也容易受到损坏。在这份手稿中,我们总结了有关开发全面协议,实验程序以及对高度可靠的铜线键合工艺和用于先进硅节点技术的线键合器件的材料清单进行详尽描述的工作。这项工作包括将该开发过程应用于整个过程和材料选择的多个方面,包括但不限于:i)在三个不同装配供应商拥有的五个不同制造地点进行铜丝键合工艺开发; ii)三种不同的模塑料; iii)三种不同的包装类型; iv)多个集成电路设计,所有电路都在焊盘下方。还总结了整个工作过程中完成的广泛的可靠性评估。使用这些详尽的协议,实验程序,特征和可靠性研究,我们成功开发了一种健壮的焊盘设计,该设计与引线键合工艺和材料清单相结合,可在先进的硅技术节点中实现高度可靠的Cu引线键合器件。

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