Novel Stacked Floating Fin Structure Gate-All-Around Field-Effect Transistor for Design and Power Optimization

摘要

Due to high power density of stacked nanosheet gate-all-around field-effect transistor (GAAFET), device structure should be optimized. In this paper, an optimized nanosheet (NS) transistor based on inverter cell structure to reduce capacitance for low power operation is proposed and analyzed. The impact of the proposed structure on the device characteristic is analyzed through simulated power, performance and area (PPA) analysis. And capacitance variation induced by stacked NS GAAFET is also analyzed.