STEADY-STATE CHARACTERIZATION OF PARTIALLY-DEPLETED SOI CMOS GATES

摘要

In this paper we deal with the steady-state behavior of a simple digital cell in partially depleted SOI technology. Because of the well-known history effects, the CMOS gates exhibit variable propagation delays from the DC conditions to the AC equilibrium obtained for periodic signals. The dependency of steady state on the signal characteristics and on other process or design parameters is analyzed for the first time.