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Marching to the beat of Moore's Law

机译:迈向摩尔定律的步伐

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Area density scaling in integrated circuits, defined as transistor count per unit area, has followed the famous observation-cum-prediction by Gordon Moore for many generations. Known as "Moore's Law" which predicts density doubling every 18-24 month, it has provided all important synchronizing guidance and reference for tools and materials suppliers, IC manufacturers and their customers as to what minimal requirements their products and services need to meet to satisfy technical and financial expectations in support of the infrastructure required for the development and manufacturing of corresponding technology generation nodes. Multiple lithography solutions are usually under considerations for any given node. In general, three broad classes of solutions are considered: evolutionary - technology that is extension of existing technology infrastructure at similar or slightly higher cost and risk to schedule; revolutionary - technology that discards significant parts of the existing infrastructure at similar cost, higher risk to schedule but promises higher capability as compared to the evolutionary approach; and last but not least, disruptive -approach that as a rule promises similar or better capabilities, much lower cost and wholly unpredictable risk to schedule and products yields. This paper examines various lithography approaches, their respective merits against criteria of respective infrastructure availability, affordability and risk to IC manufacturer's schedules and strategy involved in developing and selecting best solution in an attempt to sort out key factors that will impact the decision on the lithography choice for large-scale manufacturing for the future technology nodes.
机译:集成电路的面积密度缩放(定义为每单位面积的晶体管数)已沿用了戈登·摩尔(Gordon Moore)著名的观测和预测技术,至今已有很多代人了。它被称为“摩尔定律”,它预测密度每18-24个月就会增加一倍,它为工具和材料供应商,IC制造商及其客户提供了有关产品和服务需要满足的最低要求的所有重要同步指导和参考。支持相应技术生成节点的开发和制造所需的基础设施的技术和财务期望。对于任何给定的节点,通常都会考虑采用多种光刻解决方案。一般而言,考虑了三大类解决方案:演化-技术是对现有技术基础结构的扩展,其成本近似或略高,且具有计划风险。革命性的-与进化方法相比,以相似的成本丢弃现有基础结构的重要部分的技术,具有较高的调度风险,但具有更高的功能;最后但并非最不重要的一点是破坏性方法,通常保证具有相似或更好的功能,更低的成本以及时间表和产品良率完全不可预测的风险。本文研究了各种光刻方法,并根据各自的基础设施可用性,可承受性和集成电路制造商的时间表以及制定和选择最佳解决方案的策略所带来的风险,评估了各自的优缺点,以试图找出将影响光刻选择决定的关键因素。用于未来技术节点的大规模生产。

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