Is Manufacturability with Double Patterning a Burden on Designer? Analysis of Device and Circuit Aspects

摘要

Pitch-splitting type of double-patterning lithography is a necessity for critical layers for sub-22 nm technologies. Double patterning lithography techniques require additional masks to manufacture a single device layer. Consequently, double-patterning lithography brings overlay as a challenge that introduces additional variability to gate-to-contact coupling capacitances, device lengths, and contact resistances. These additional variability sources may negatively impact circuit performance. In this work, we provide analysis of digital and analog circuit blocks designed in 20 nm. We demonstrate the impact due to overlay-impacted change in resistance of self-aligned contacts. Furthermore, we provide layout optimization guidelines to reduce the impact of overlay. We demonstrate our methodology using TCAD and circuit simulations. We show that overlay impact may not be negligible, and pessimism reduction techniques should utilize suggested analysis and optimization methods.