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Alternative approaches implementing high-performance FIR filters on lookup-table-based FPGAs: a comparison

机译:在基于查找表的FPGA上实现高性能FIR滤波器的替代方法:比较

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Abstract: Finite impulse response filters (FIR filters) are verycommonly used in digital signal processing (DSP)applications and are traditionally implemented usingASICs or DSP-processors. For FPGA implementation, dueto the high throughput rate and large computationalpower required under real-time constraints, they are achallenging subject. Indeed, the limitation ofresources on FPGA, i.e., logic blocks and flip flops,and furthermore, the high routing delays, requirescompact implementations of the circuits. Threeapproaches for implementation of high-performancesymmetric FIR filters on lookup table-based FPGAs willbe considered in this paper. Fully parallel distributedarithmetic, table lookup multiplication, andconventional hardware multiplication. Implementationresults will be illustrated by an 8 taps 8 bitssymmetric FIR filter, and comparative considerations ofthe above approaches invoked for Xilinx FPGAs will bealso shown.!9
机译:摘要:有限脉冲响应滤波器(FIR滤波器)通常用于数字信号处理(DSP)应用中,传统上是使用ASIC或DSP处理器实现的。对于FPGA实施,由于实时约束下所需的高吞吐率和巨大的计算能力,它们是具有挑战性的主题。实际上,FPGA上的资源(即,逻辑块和触发器)的局限性以及高布线延迟都要求电路的紧凑实现。本文将考虑在基于查找表的FPGA上实现高性能对称FIR滤波器的三种方法。完全并行的分布式算术,表查找乘法和常规硬件乘法。实施结果将通过一个8抽头8位对称FIR滤波器进行说明,并且还将显示对Xilinx FPGA调用的上述方法的比较考虑。9

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