Pattern Distortion of a Stencil Reticle Caused by Stress of Silicon Membrane and Resist on the Reticle

摘要

Silicon stencil reticle has been developing for the EB stepper, which is the electron beam projection lithography system for 70nm node generation and beyond. The reticle distortion is affected by stress such as silicon membrane stress and resist stress on a reticle in their fabrication. To analyze pattern distortion using finite element method (FEM), the image placement (IP) and the critical dimension (CD) errors of the stencil reticle were measured at every step of reticle fabrication processes. It was found that the resist stress is the key factor of IP error in the membrane process. In the wafer process, the IP errors are mainly related to silicon membrane stress. IP and CD errors of 200mm stencil reticle in both processes are discussed using FEM. The calculation results show CD errors are caused by the stress of silicon membrane. Moreover, it is discussed that CD error depends on pattern shape and density even on the stress-controlled reticle blanks.