Low Power High Performance 2-D Transform Coprocessor for H.264 Video Compression Standard

摘要

This paper presents a VLSI architecture and an efficient implementation of an embedded transform coprocessor for H.264 video compression standard. The proposed coprocessor was designed to work with an ARM946E-S processor. To enhance the performance, both data parallelism and pipelined architecture are utilized in the design. In this study, coprocessor was synthesized with 0.18μm CMOS technology and its footprint is only 0.0838 mm~2. Coprocessor can calculate 2-D transform for a macroblock in 30 clock cycles. The 2-D transform coprocessor dissipates 529μW with 1.55-volt power supply at 10 MHz clock rate.