AN FPGA BASED CO-PROCESSOR FOR ELLIPTIC CURVECRYPTOGRAPHY

摘要

This paper describes an FPGA based hardware acceleratorrnfor elliptic curve cryptography. This accelerator performsrnbinary polynomial basis operations in Galois Field GFrn( 2m) using a microcoded structure. Microcoderninstructions support basic Galois Field operationsrnregardless of encryption algorithms or keys. It uses arnpipeline bit-serial architecture for the mostrncomputationally intensive Galois field operation (I.e.,rnmultiplication) with reduction. Due to its bit-serialrnarchitecture, it has regular structure, low powerrnconsumption, low cost area and a reduced number of pinsrnwhich makes it suitable for hand held devicesrnapplications. For speeding up the design, we use thernmulti-word operand structure while it decreases the I/Ornpin requirements. In addition, a simple technique is usedrnfor immediate Galois field addition/subtraction operationrnto speed up the design further. The design is implementedrnin VHDL and the Xilinx ISE 8.2 and Modelsim XE arernused for implementation and simulation, respectively. Thernclock frequency of design is around 180 MHz which canrnperform a scalar multiplication over GF (2m ) in 1.1 μSec.