Masking power usage of co-processors on field-programmable gate arrays using negative feedback to adjust a voltage variation on an FPGA power distribution trace

摘要

Technologies are generally described for masking power usage of co-processors on field-programmable gate arrays. In some examples, one or more moat brick circuits may be implemented around a co-processor loaded on a held-programmable gate array (FPGA). The moat brick circuits may be configured to use negative feedback and/or noise to mask the power usage variations of the co-processor from other co-processors on the FPGA.