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MASKING POWER USAGE OF CO-PROCESSORS ON FIELD-PROGRAMMABLE GATE ARRAYS
MASKING POWER USAGE OF CO-PROCESSORS ON FIELD-PROGRAMMABLE GATE ARRAYS
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机译:在现场可编程门阵列上利用协同处理器的功率
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摘要
Technologies are generally described for masking power usage of co-processors on field- programmable gate arrays. In some examples, one or more moat brick circuits may be implemented around a co-processor loaded on a field-programmable gate array (FPGA). The moat brick circuits may be configured to use negative feedback and/or noise to mask the power usage variations of the co-processor from other co-processors on the FPGA.
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