The Study of Dry Etching Process on Plasma Induced Damage in Cu Interconnects Technology

摘要

As complementary metal-oxide-semiconductor (CMOS) is rapidly shrunk and the plasma processing steps are increased in number at 65nm node and beyond, plasma-induced damage (PID) has become a serious reliability problem in state-of-the-art semiconductor manufacturing. In this paper, we only focus on the PID issues originating from the dry etching processes in back-end-of-the-line and utilize the in-line test structure to in-situ debug the possible PID impact from the specific layer. The effects of various etching process parameters such as power, power frequency, magnetic field and process time are examined. Results demonstrate metal 1 (Ml) etch, passivation etch and Al-pad etch play the critical role in PID performance on the given test vehicles. Nevertheless, their sensitivities are quite different between N-MOS and P-MOS. Basically, N-MOS degradation strongly depends on Al-pad etch while P-MOS PID performance is closely related to Ml etch and passivation etch. More specifically, the over-etch percentage in Ml etch is one of effective knobs in alleviating PID while it is not in passivation etch. All the above discrepancies indicate the single PID failure mechanism could not be applied. We tentatively explain the existing phenomena from the point of view of electron shading effect (ESE), reverse electron shading effect (RESE), plasma non-uniformity, photo-conductive effect and ultra-thin charging collector during the interface switch in etching.