Reliability issues on the 128M TSOP II 54L dual chip package

摘要

The ChipMOS proprietary package, TSOP II 54L Dual Chip 128M SDRAM, combines two 0.2#mu#m process dice in a single chip. Together with a BT based two-layer substrate for interconnections and Hitachi~(circle R) film provides the adhesive force. From the study it can be found that the bonding conditions between the film and substrate dominate the reliability of the package. However, the reliability is not only related to the adhesive material but also depends on the quality of the substrate. This paper indicates the techniques used for this package with the experiments applied on the subjects as (1) Taping on substrate, (2) Substrate warpage control, (3) Planarity taping, and (4) The related reliability improvements. The analyses made in order to support the decision-making are focused mainly on the substrate and film materials. All the efforts devoted on the package development have concluded a good outcome and the product is formally pass JEDEC Level III in reliability. Level III in reliability.