Process Development and Resist Modification for Metal Trench Layers from 65nm to 45 nm Nodes

摘要

A combination of simulation, resist modification and process optimization were used to develop production worthy dry 193nm lithography processes, suitable for the metal trench layers of 65nm node logic devices. The important performance characteristics of a back-end metal trench layer are through-pitch proximity bias, lithographic latitude and ultimate resolution. Simulation results suggested that a moderate annular illumination setting balances proximity bias against resolution at the forbidden pitch, yielding a good overall through-pitch common process window. Resist material optimization through resin, PAG (photo-acid generator) and base quencher modification improves proximity bias and results in excellent lithographic performances of good LER (line edge roughness), low MEF (Mask Error Factor) and wider process latitude. To investigate extendibility to 45nm node applications, the immersion compatibility of the optimized resist with several top coats are reported.