Study of Hysteresis in Vertical Ge-Source Heterojunction Tunnel-FETs at Low Temperature

摘要

This work studies the hysteresis behaviour in vertical Ge-source gate all-around tunnel field-effect transistors (TFETs) at low temperature. Two devices with different HfO_2 thickness in the gate stack (2nm and 3nm) are compared. The goal is to investigate the impact of oxide trapping on the trap-assisted tunneling. It is shown that there is only a minor effect - the main impact of gate oxide trapping is the shift in the onset voltage of the TFET, through a charge-trapping-induced shift in the flat-band voltage.