FPLD implementation of computation over finite fields GF(2~m) with applications to error control coding

摘要

This paper investigates the implementation of computations over finite fields GF(2~m) using field-programmable logic devices (FPLDs). Implementation details for addition/subtraction, multiplication, square, inversion, and division are given with mapping results for Xilinx LCAs, Altera CPLDs and Actel ACT FPGAs. As an application example, mapping results for complete encoders for error-correcting codes are also presented. Finally, new opportunities emerging from FPLD technology for data transmission systems with dynamic code adaption are discussed.