3-D thin chip integration technology - from technology development to application

摘要

3-D technologies open a wide range of chip integration possibilities for microelectronic systems. Most of these technologies are using Through-Silicon Vias (TSV). One disadvantage of this technology is the high investment for new equipment and processing cost for Si etching and metallization. The thin chip integration technology (TCI) presented in this paper is based upon existing WLP infrastrcuture: The core component of this planar integration technology is the embedding of ultra-thin chips into a multi layer thin film routing on a larger sized substrate chip on wafer level. All process steps are performed with standard back end equipment used for redistribution and other wafer level packaging technologies. Using advanced grinding and etching technologies thinning of CMOS chips is possible down to a thickness of 20 to 40 microns with high yield. These ultra-thin chips can be integrated into BCB-copper multi layer redistribution on wafer level.