A route towards production-worthy 5 µm × 25 µm and 1 µm × 20 µm non-Bosch through-silicon-via (TSV) etch, TSV metrology, and TSV integration

摘要

We report a process development route towards 300 mm production-worthy non-Bosch through-silicon-via (TSV) etch with critical dimensions and via spacing between 1–5 µm and aspect ratios (ARs) up to 20∶1 for 3D logic integration. This was performed on an experimental alpha-tool from Tokyo Electron: a magnetically enhanced capacitively coupled plasma etcher with a dipole ring magnet upgrade that aims to capture the strengths (anisotropicity, profile uniformity) while reducing the weaknesses (scalloping, undercut, residues) of a nominal Bosch process. Trending experiments were performed to understand key modulators that contribute to the control of sidewall taper and roughness, etched TSV volume and depth, mask undercut, local bowing effects, and within wafer (WIW) center-to-edge depth and profile uniformity. Selected process-of-records in fabricating TSVs with nominal sizes of 5 µm × 25 µm, 5 µm × 40 µm and 1 µm × 20 µm with ∼ 1 % WIW depth uniformity, negligible silicon scalloping/mask undercut, and good profile control were developed. These include vertical TSVs and tapered TSVs for different 3D wafer stacking applications. For TSV metrology, assessments were conducted using wafer thickness sensor technology (Tamar Technology, Inc) that is not limited by AR: an optical, non-invasive, and high throughput sensor that measures the etched depth of vias using backside IR illumination. In having a continuous 2kÅ TEOS oxide liner/100 Å Ta(TaN) barrier/5kÅ Cu seed stack enabled by TSV etch, Cu-filled TSVs of 3 µm × 20 µm and 5 µm × 25 µm were demonstrated.