Low-voltage 0.35 μm CMOS/SOI technology for high-performanceASIC's

摘要

A 0.35 μm CMOS process for low-voltage, high-performancenASIC's, implemented on ultra-thin SOI (Shallow SIMOX) wafers, isndescribed. Stable high speed, low-Vth transistors for low-voltagenoperation at 1.5v are integrated in a salicided dual-gate process.nShallow SIMOX devices dissipate 1/5 of the Bulk-Si power. A prototypenPLL circuit operates at fmax of 1.6 GHz at 1.5v supply voltage,ndemonstrating the excellent performance of this technology