RPN Oxynitride Gate Dielectrics for 90 nm Low Power CMOS Applications

摘要

This paper investigates the use of RPN-based oxynitride gate dielectrics for 90 nm Low Power (LP) CMOS applications. Several recipes have been developed to optimise the gate dielectric for targeted EOT, high mobility and improved EOT uniformity. Compared to conventional furnace oxynitride, significant gate leakage reduction has been found in devices with plasma nitrided oxides. This enabled reaching the spec for the I_(OFF) current of 20 pA/μm and improve theI_(ON)-I_(OFF) trade-off. The I_(ON) current obtained at 1.2 V for NMOS and PMOS devices is 427 μA/μm (at I_(OFF) =16 pA/μm) and 170 μA/ μm (at I_(OFF =16 pA/μm), respectively. The obtained results are among the best values reported in the literature.