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Lateral Trench Gate Super-Junction SOI-LDMOSFETs with Low On-Resistance

机译:具有低导通电阻的横向沟槽栅极超结SOI-LDMOSFET

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This paper describes low on-resistance lateral trench gate super-junction LDMOSFETs on SOL The specific on-resistance (R_(sp)) of the SOI-LDMOSFETs is effectively improved by the super-junction concept together with the lateral trench gate. The super-junction helps to increase the doping concentration of the n-drift layer, and the lateral trench gate allow to increase the channel area. It can be achieved to reduce the on-resistance both of the n-drift and channel regions, respectively. Using the three-dimensional numerical simulator MINIMOS-NT, we confirm that the R_(sp) of the proposed lateral trench gate super-junction SOI-LDMOSFETs is about 60% of conventional SOI-LDMOSFETs. With the larger n column width than that of the p column the doping in the drift region can be reduced to 70% of the value of standard super-junction devices without degrading the on-resistance. As a result the sensitivity of the breakdown voltage to the charge imbalance can he improved in the proposed device.
机译:本文介绍了基于SOL的低导通电阻横向沟槽栅极超结LDMOSFET。通过超结概念与横向沟槽栅极一起有效地提高了SOI-LDMOSFET的比导通电阻(R_(sp))。超结有助于增加n型漂移层的掺杂浓度,而横向沟槽栅可以增加沟道面积。可以实现分别减小n漂移区和沟道区两者的导通电阻。使用三维数值仿真器MINIMOS-NT,我们确认了所提出的横向沟槽栅超结SOI-LDMOSFET的R_(sp)约为传统SOI-LDMOSFET的60%。如果n列的宽度大于p列的宽度,则可以将漂移区中的掺杂降低到标准超结器件值的70%,而不会降低导通电阻。结果,在所提出的装置中可以提高击穿电压对电荷不平衡的敏感性。

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