Receiver Chip in 0.6#xb5;m BiCMOS with AGC and LVDS Output Driver

摘要

An integrated receiver chip for external photodiodes (PDs) is presented in 0.6-μm BiCMOS technology with 3.3-V supply voltage. It consists of an internal automatic gain control (AGC), which simultaneously compensates the frequency characteristics, an internal charge pump, which delivers optionally 5 V to external PDs, a detector to show whether data is received and a 50Ω differential output driver for LVDS (low voltage differential signaling) logical standard. The chip was tested electrically without PD as well as with the commercially available PIN PDs S5973 (Hamamatsu) and PS0.25-5 SMD (Silicon Sensor International AG). The power consumption amounts to 113 mW and a maximum data rate of 3.2 Gb/s was measured electrically, where a current sensitivity (BER = 10^-̅9) of 21 μA mean input current was achieved. At 1.25 Gb/s a current sensitivity of 4.1 μA was measured. With external PDs bonded to the receiver the optical sensitivity was -14.7 dBm (1.25 Gb/s, λ = 780 nm) for S5973 and -20.3dBm (1Gb/s, λ=850nm) mean optical power at the input for PS0.25-5 SMD. With these results the receiver chip might be a low-cost alternative for plastic optical fiber (POF) receivers, optical LAN, data comm receivers or for optical wireless communication (OWC) receivers. To achieve higher sensitivities, an external avalanche photodiode (APD) could be connected easily to the receiver chip instead of PIN PDs.