Effect of scaling copper through-silicon vias on stress and reliability for 3D interconnects

摘要

In this paper, the scaling effect on copper TSV stress and reliability is investigated, focusing on the correlation of microstructure with plasticity and extrusion for 10, 5, and 2¿¿m diameter vias, fabricated by the via middle process. X-ray microdiffraction revealed local plasticity in the tops of the vias for all sizes, and showed that this seemed to depend on the variations in the grain structure. The microstructure showed a tight distribution of grain sizes after the post-plating anneal, but further annealing caused considerable spreads for all via diameters. This trend is consistent with the via extrusion statistics observed, where the absolute values and variation in the extrusion heights increased significantly with annealing. Overall, these results suggest that scaling down TSV dimensions may not improve the stress and reliability behavior, particularly after further annealing at 400¿¿C. Since such annealing processes are required for via-middle fabrication, it seems that via reliability will continue to be a challenge as TSV scaling continues.