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Cu pillar bump flip chip package development for advanced node chip

机译:用于高级节点芯片的铜柱凸点倒装芯片封装开发

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摘要

In this work, the 14 nm CPI (Chip and Package Interaction) challenges, development and qualification were investigated by using 130 um pitch Cu pillar bump in flip chip BGA package without heat spreader. We evaluated 14 nm BEOL film strength and adhesion in the torture tests. After passing the torture tests, the package is evaluated in the CPI reliability tests following the JEDEC standard. We optimized the package structure, process and BOM (Bill of Materials) to find compatible package solutions and checked the robustness of die seal ring structure. After the reliability tests, SAM (Scanning Acoustic Microscope) and typical electrical test were conducted to confirm any failures. Moreover, SEM (Scanning Electron Microscope) and FIB (Focused Ion Beam) were used to confirm the defect mode. A 3D thermal-mechanical finite element model was built to analyze the stress field for early material assessment, selection and structure optimization. The simulation results revealed that larger bump, small PI opening, and high Tg (Glass Transition Temperature) underfill reduced more stress on BEOL film stack. CPI formal qualification showed all samples passed reliability tests and no side-wall crack, bump / ULK crack and delamination after assembly process and CPI tests. We have successfully demonstrated the CPI solution for 14 nm chip using Cu pillar bump in flip chip package.
机译:在这项工作中,通过在不带散热器的倒装芯片BGA封装中使用130 um间距的铜柱凸点,研究了14 nm CPI(芯片和封装相互作用)的挑战,发展和资格鉴定。在酷刑测试中,我们评估了14 nm BEOL膜的强度和附着力。通过酷刑测试后,将按照JEDEC标准在CPI可靠性测试中对包装进行评估。我们优化了封装结构,工艺和BOM(物料清单),以找到兼容的封装解决方案,并检查了模具密封环结构的坚固性。经过可靠性测试后,进行了SAM(扫描声显微镜)和典型的电气测试,以确认是否有故障。此外,使用SEM(扫描电子显微镜)和FIB(聚焦离子束)确认缺陷模式。建立了一个3D热机械有限元模型来分析应力场,以进行早期材料评估,选择和结构优化。仿真结果表明,较大的凸点,较小的PI开口和较高的Tg(玻璃化温度)底部填充可减少BEOL膜叠层上的更多应力。 CPI正式鉴定表明,所有样品均通过了可靠性测试,并且在组装过程和CPI测试之后没有侧壁裂纹,凸起/ ULK裂纹和分层。我们已经成功演示了使用倒装芯片封装中的Cu柱形凸点的14 nm芯片CPI解决方案。

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