首页> 外文会议>2014 26th International Conference on microelectronics >Low-leakage 9-CN-MOSFET SRAM cell with enhanced read and write voltage margins
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Low-leakage 9-CN-MOSFET SRAM cell with enhanced read and write voltage margins

机译:具有增强的读写电压裕量的低泄漏9-CN-MOSFET SRAM单元

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摘要

A novel static random-access memory (SRAM) cell with nine carbon nanotube MOSFETs (9-CN-MOSFETs) is proposed in this paper. With the new 9-CN-MOSFET SRAM cell, the read data stability is enhanced by 99.09% while providing similar read speed as compared to the conventional six-transistor (6T) SRAM cell in a 16nm carbon nanotube transistor technology. The worst-case write voltage margin is increased by 4.57x with the proposed 9-CN-MOSFET SRAM cell as compared to the conventional 6T SRAM cell. Furthermore, a 1Kibit SRAM array with the new memory cells consumes 34.18% lower leakage power as compared to the memory array with 6T SRAM cells in idle mode.
机译:本文提出了一种新型的带有九个碳纳米管MOSFET(9-CN-MOSFET)的静态随机存取存储器(SRAM)单元。与采用16nm碳纳米管晶体管技术的传统六晶体管(6T)SRAM单元相比,新型9-CN-MOSFET SRAM单元的读取数据稳定性提高了99.09%,同时提供了相似的读取速度。与传统的6T SRAM单元相比,建议的9-CN-MOSFET SRAM单元在最坏情况下的写电压裕度提高了4.57倍。此外,与具有6T SRAM单元的存储阵列处于空闲模式相比,具有新存储单元的1Kibit SRAM阵列的泄漏功率降低了34.18%。

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