Methodology for extracting the characteristic capacitances of a power MOSFET transistor, using conventional on-wafer testing techniques

摘要

A methodology for extracting the characteristic reverse transfer-, input- and output-capacitance on power MOSFET transistors is presented in this work. We show that by using standard CV setup and measurement techniques, these dynamic characteristics can be obtained from separate measurements of the three capacitance components: Gate-todrain, gate-to-source and drain-to-source capacitances. Our method is validated against industry-like approaches, using dedicated complex circuits and procedures. The advantage of our approach lies in its simplicity, flexibility and applicability to common electrical testing equipment and holds both for wafer level and package level characterization.