A verification methodology for the detection of spectrally efficient FDM signals generated using reconfigurable hardware

摘要

Simulation, using a model of a system or process, is widely accepted as a method of qualification and evaluation of complex systems. The success of a simulation depends on the accuracy of user defined values used to model parameters, which are gathered by analytical or empirical methods. In situations where some parameters are unknown or difficult to quantify, it is required to perform those operations in a real-world situation. Often, moving from a simulation environment to a hardware environment can result in considerable development and implementation challenges. Hence, simulation in conjunction with hardware, so called in the loop validation, can provide a fast method for verification and a reduction in development time. This paper concerns the successful signal transmission and reception of a recently proposed communication scheme, termed as Spectrally Efficient Frequency Division Multiplexing (SEFDM). Signal transmission is verified using in the loop methodology. Experimentally generated signals from a bespoke reconfigurable Field Programmable Gate Array (FPGA) are sampled, using an oscilloscope and formatted for detection using a model of the FPGA architecture together with an analytical model of the SEFDM transmitter. Subsequently, such signals form the input to an analytical receiver model which is used to confirm the experimental signals and hence, exemplifies the in the loop methodology to form an SEFDM pseudo-transceiver.