Theoretical investigation of back gate bias effect on the electrostatic integrity of Insulated Shallow Extension Silicon On Void (ISESOV) MOSFET

摘要

The present work discusses the electrostatic integrity of Insulated Shallow Extension Silicon On Void (ISESOV) MOSFET examine by calculating the 2D potential in the channel region using Poisson's equation. The complete drain current model incorporating velocity overshoot effect and the Channel Length Modulation effect (CLM) has also been developed for channel length down to 32nm. Furthermore, the impact of back gate bias voltage (forward and reverse both) on the sub-threshold performance, drain current and inverter performance has also been studied.