Dual-edge triggered sense amplifier flip-flop utilizing an improved scheme to reduce area, power, and complexity

摘要

In this paper, we propose a dual-edge sense amplifier flip-flop (DE-SAFF) using an improved clocking scheme to reduce area, power, and complexity. The proposed scheme does not require any changes on the single-edge flip-flop to enable dual-edge triggering. The extracted circuit layout of the proposed DE-SAFF has been simulated in TSMC 65-nm technology at a frequency of 2.5 GHz and a throughput of 5 GHz. Simulation results show correct functionality of the proposed flip-flop under process, voltage, and temperature (PVT) variations. Comparing the proposed DE-SAFF to other flip-flops, show that in addition to reduced design complexity, the proposed flip-flop has low power consumption and a lower area.