首页> 外文会议>2010 IEEE International Behavioral Modeling and Simulation Workshop >Fast dynamic simulation of VLSI circuits using reduced order compact macromodel of standard cells
【24h】

Fast dynamic simulation of VLSI circuits using reduced order compact macromodel of standard cells

机译:使用标准单元的降阶紧凑宏模型对VLSI电路进行快速动态仿真

获取原文
获取原文并翻译 | 示例

摘要

This paper presents a dynamic simulation methodology using a reduced order compact macromodel of standard cells. The standard cell macromodels are formulated with a smaller number of state variables compared to an equivalent transistor-level implementation. This results in significant speed-ups over transistor-level simulation for large scale circuits. Such reduction in state variables also reduces memory usage. The macromodels are based on transistor equations, and simulation using these models produces results in excellent agreement (delay errors below 1%) with transistor-level simulation results. Various examples showing 1.5x−100x reduction in dynamic simulation time and 1.5x−2.8x reduction in memory usage are presented.
机译:本文提出了一种使用标准单元的降阶紧凑宏模型的动态仿真方法。与等效的晶体管级实现相比,标准单元宏模型用较少数量的状态变量来表示。与大规模电路的晶体管级仿真相比,这可以显着提高速度。状态变量的这种减少也减少了内存使用。宏模型基于晶体管方程,使用这些模型进行的仿真得出的结果与晶体管级仿真结果具有极好的一致性(延迟误差低于1%)。给出了各种示例,这些示例显示了动态仿真时间减少了1.5x-100x,内存使用减少了1.5x-2.8x。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号