A 3D SOI SRAM Suitable for Processor Integration

摘要

One of the interconnection related challenges that face future computer designers is the so called "memory wall." While currently marketed processor clock rates have temporarily stalled, and multiple core microprocessors are growing in importance, there is no escape from the memory wall. The peak processor performance using either single high clock rate, or multiple core slower clock rate systems, will doubtless create the same amount of demand on memory especially if the multiple cores need access to one shared memory address space. It will be the total demand upon this memory in bytes per second that limits performance regardless of the source of this demand. The widening gap between this total processor demand and what real memory can sustain constitutes the memory wall. Current on chip memory such as L1 or L2 cache demonstrates the advantage of ultra short wiring in reducing latency. But eventually access must be to L3 or other main memory, which traditionally requires a multiple chip solution. Conventional packaging increases wiring capacitance to these distant chips, limits bus bit bandwidth, and demands additional power consumption for pad drivers. 3D integration of SRAM, and eventually DRAM, can facilitate much wider bus bit bandwidth and reduce latency for these higher-level cache memories. Long external interconnections can be then reduced to extremely short, low parasitic, low driver power demand, low-skew vertical vias. For extremely small lateral dimensions these vertical vias can be packed very tightly, presenting the opportunity for much larger numbers of data and address lines to pass between the processor and memory.