The method includes forming an integrated circuit on a front surface of a first chip, performing backside grinding on the first chip to expose a plurality of through vias in the first chip; and forming a first bridge structure on the back surface of the first chip using a damascene process. The first bridge structure includes a first bond pad, a second bond pad, and a conductive trace electrically connecting the first bond pad to the second bond pad. The method further includes bonding a second chip and a third chip to the first chip via face-to-back bonding. A third bond pad of the second chip is bonded to the first bond pad of the first chip. A fourth bond pad of the third chip is bonded to the second bond pad of the first chip.
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